JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.

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A printed circuit board assembly with components mounted on top and bottom sides jwsd22 the board. This may require additional boards to be tested to achieve the sample sizes given above.

Additional strain gages may also be mounted at jrsd22 locations on the board to fully characterize the strain response of the assembly. The fundamental mode results in maximum displacements and is typically most damaging.

The board assembly shall then be mounted on the drop test fixture using four screws. The board shall still be designed as double-sided with footprint of similar sized components on each side. The test boards shall be assembled using best known methods of printed circuit assembly jedd22, representative of production methods.


It is recommended that the component mounting pads on the PCB be designed as per the specification in Table 3 for area array devices. There shall be 20 plated through holes per square centimeter in the component region. The high-speed data acquisition system should be able to measure resistance with a sampling rate of 50, samples per second or greater. Experiments with different strike surface may be needed to achieve the desired peak value and duration. All components used for this testing must be daisy-chained.


Both accelerometer and stain gage shall be connected to data acquisition system capable of measuring at a scan frequency of 20 kHz and greater with a 16 bit signal width. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.

Board thickness, warpage, and pad sizes shall also be measured using a sampling plan. The electrical resistance of each 1b11 shall be measured in-situ during each drop and all failures shall be logged.

However, a mix of different component sizes and styles shall not be used on the same board, as this will jes2d2 the dynamic response of the board, making the results difficult to analyze.

Because of symmetric component design and support locations, grouping see Table 6 can be used for data analysis for boards mounted with 15 components refer Figure 1. The PCB assembly shall be mounted to the base plate standoffs using 4 screws, one at each corner of the board.

The die size and thickness should be similar to the functional die size to be used in application. The glass transition temperature, Tg, of each dielectric material as well as of the composite board shall be oC or greater. Depending on the strike surface, same drop height may result in different G level and pulse duration.

A printed circuit board assembly with components mounted on only one side of the board double-sided PCB assembly: During the test, the shock pulse shall be measured for each drop to ensure that input pulse remains within the specified tolerance.

The drop test shall be conducted by releasing the drop table from the pre-established height.


JESDB B Board level drop test menthod of components for handheld eletronic products_百度文库

This is not jesd222 component qualification test and is not meant to replace any system level drop test that maybe needed to qualify a specific handheld electronic product. Similarly, a larger group containing components in Group B and D may also exist. The event detector should be able to detect any intermittent discontinuity of resistance greater than ohms lasting for 1 microsecond or longer.

The through holes shall have the drill diameter of microns and finished plated hole diameter of microns. Table 1 provides the thickness, copper coverage, and the material for each layer.

The method is applicable to both area-array and perimeter-leaded surface mounted packages. Since the drop performance is a function of component location on the board, testing with components mounted on all 15 locations will provide useful information to the users of this data OEMs in proper layout of their product board.

The maximum acceleration during the dynamic motion of the test apparatus. Although daisy-chain nets will typically not require plated though holes PTH other than those required for manual probe pads and connectors, the test board shall contain PTH in the component region 1.


All failures after each drop shall be logged. Organizations may obtain permission to reproduce a limited number jwsd22 copies through entering into a license agreement. This shall be accomplished by designing double sided boards with mirror component footprint on each side top and bottom of the board.